1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a NAND ROM.
2. Description of the Prior Art
In recent years integration levels of MOS semiconductor integrated circuits have been becoming markedly higher and higher.
With increasing integration level, MOS-transistor NAND ROMs are moving from 32- to 64-Mbit memory capacity per chip.
A NAND ROM comprises unit arrays consisting of rows of memory transistors connected in series and being connected through unit selective transistors between digit lines and ground lines. It is common that on a semiconductor chip are arranged a plurality of cell array blocks each comprises a number of parallel digit lines running in the column direction. Along each digit line, one or two rows of unit arrays are disposed.
For MOS devices, previously the local oxidation technique was used for isolation between the above-mentioned unit array rows. Recently it has been replaced by the trench isolation technique. The trench isolation technique involves building, on a semiconductor chip, trenches having a predetermined-width, and, after forming a silicon oxide film over the surface of them, filling them with an insulating material such as BPSG film. The size, especially width, of the thus-built device isolation structures is one of major factors limiting integration levels of NAND ROMS because they are limited to the minimum feature size involving the lithography technique. For example, letting the minimum feature size be 0.4 .mu.m, the space between unit array rows is not allowed to be set smaller than this size.